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october 2008 rev 16 1/59 1 m25p40 4 mbit, low voltage, serial flash memory with 75 mhz spi bus interface features ? 4 mbit of flash memory ? 2.3 v to 3.6 v single supply voltage ? spi bus compatible serial interface ? 75 mhz clock rate (maximum) ? page program (up to 256 bytes) in 0.8 ms (typical) ? sector erase (512 kbit) in 0.6 s (typical) ? bulk erase (4 mbit) in 4.5 s (typical) ? deep power-down mode 1 a (typical) ? hardware write protection: protected area size defined by three non-volatile bits (bp0, bp1 and bp2) ? electronic signatures ? jedec standard two-byte signature (2013h) ? unique id code (uid) with 16 bytes read- only, available upon customer request ? res instruction, one-byte, signature (12h), for backward compatibility ? packages ? ecopack? (rohs compliant) so8w (mw) 208 mils width so8 (mn) 150 mils width qfn8l (ms) mlp8 6 x 5 mm vfqpn8 (mp) (mlp8 6 x 5 mm) www.numonyx.com
contents m25p40 2/59 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 serial data output (q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 serial data input (d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 serial clock (c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 chip select (s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 hold (hold ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.6 write protect (w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.7 v cc supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.8 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 spi modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 sector erase and bulk erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . 12 4.4 active power, standby power and deep power-down modes . . . . . . . . . 12 4.5 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.6 protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.7 hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 write enable (wren) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.2 write disable (wrdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.3 read identification (rdid) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.4 read status register (rdsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.4.1 wip bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.4.2 wel bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.4.3 bp2, bp1, bp0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
m25p40 contents 3/59 6.4.4 srwd bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.5 write status register (wrsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.6 read data bytes (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.7 read data bytes at higher speed (fast_read) . . . . . . . . . . . . . . . . . . 27 6.8 page program (pp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.9 sector erase (se) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.10 bulk erase (be) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.11 deep power-down (dp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.12 release from deep power-down and read electronic signature (res) . 33 7 power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 11 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
list of tables m25p40 4/59 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. protected area sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3. memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 4. instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 5. read identification (rdid) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 6. status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 7. protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 8. power-up timing and v wi threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 9. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 10. operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 11. data retention and endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 12. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 13. dc characteristics (device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 14. dc characteristics (device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 15. instruction times, process technology t9hx (device grade 6) . . . . . . . . . . . . . . . . . . . . . . 40 table 16. instruction times, process technology t7y (device grade 6) . . . . . . . . . . . . . . . . . . . . . . . 41 table 17. instruction times (device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 18. ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 19. ac characteristics (25 mhz operation, device grade 3, v cc min = 2.7 v) . . . . . . . . . . . . . 43 table 20. ac characteristics (50 mhz operation, device grade 6, v cc min = 2.7 v) . . . . . . . . . . . . . 44 table 21. ac characteristics (*40 mhz operation, device grade 6, v cc min = 2.3 v) . . . . . . . . . . . . 45 table 22. ac characteristics, grade 6 (t9hx technology), 75 mhz operation, vcc min = 2.7 v . . . 46 table 23. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 24. so8 wide ? 8 lead plastic small outline, 208 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 25. qfn8l (mlp8) 8-lead dual flat package no lead, 6 x 5 mm package mechanical data . . . 51 table 26. vfqfpn8 (mlp8) 8-lead very thin fine pitch quad flat package no lead, 6 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 27. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 28. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
m25p40 list of figures 5/59 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. so and mlp8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. bus master and memory devices on the spi bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. spi modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 6. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 7. write enable (wren) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 8. write disable (wrdi) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 9. read identification (rdid) instruction sequence and data-out sequence . . . . . . . . . . . . . 22 figure 10. read status register (rdsr) instruction sequence and data-out sequence . . . . . . . . . . 23 figure 11. write status register (wrsr) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 12. read data bytes (read) instruction sequence and data-out sequence . . . . . . . . . . . . . . 26 figure 13. read data bytes at higher speed (fast_read) instruction sequence and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 14. page program (pp) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 15. sector erase (se) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 figure 16. bulk erase (be) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 17. deep power-down (dp) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 18. release from deep power-down and read electronic signature (res) instruction sequence and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 19. release from deep power-down (res) instruction sequence . . . . . . . . . . . . . . . . . . . . . . 34 figure 20. power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 21. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 22. serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 23. write protect setup and hold timing during wrsr when srwd = 1 . . . . . . . . . . . . . . . . . 47 figure 24. hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 25. output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 26. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package outline. . . . . . . 49 figure 27. so8w ? 8 lead plastic small outline, 208 mils body width, package outline. . . . . . . . . . . . 50 figure 28. qfn8l (mlp8) 8-lead, dual flat package no lead, 6 5 mm, package outline . . . . . . . . . 51 figure 29. vfqfpn8 (mlp8) 8-lead very thin fine pitch quad flat package no lead, 6 5 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
description m25p40 6/59 1 description the m25p40 is a 4 mbit (512 k 8) serial flash memory, with advanced write protection mechanisms, accessed by a high speed spi-compatible bus. the m25p40 features high performance instructions allowing clock frequency up to 75 mhz. (1) the memory can be programmed 1 to 256 bytes at a time, using the page program instruction. the memory is organized as 8 sectors, each containing 256 pages. each page is 256 bytes wide. thus, the whole memory can be viewed as consisting of 2048 pages, or 524,288 bytes. the whole memory can be erased using the bulk erase instruction, or a sector at a time, using the sector erase instruction. in order to meet environmental requirements, numonyx offers the m25p40 in ecopack? packages. ecopack? packages are lead-free and rohs compliant. ecopack is an numonyx trademark. ecopack specifications are available at: www.numonyx.com . important: this datasheet details the functionality of the m25p40 devices, based on the previous t7y process or based on the current t9hx process (available since august 2008). the new device in t9hx is completely backward compatible with the old one in t7y and it additionaly features: - improved max frequency (fast read) to 75 mhz in the standard vcc range 2.7 v to 3.6 v, while the max frequency (fast read) in the extended vcc range 2.3 v to 2.7 v is 40 mhz - uid/cfd protection feature figure 1. logic diagram 1. 75 mhz operation is available only on the vcc range 2.7 v - 3.6 v and for process technology t9hx devices, identified by process identification digit "4" in the dev ice marking and process letter "b" in the part number. ai04090 s v cc m25p40 hold v ss w q c d
m25p40 description 7/59 figure 2. so and mlp8 connections 1. there is an exposed central pad on the underside of the mlp8 packages. this is pulled, internally, to v ss , and must not be allowed to be connected to any other voltage or signal line on the pcb. 2. see section 11: package mechanical for package dimensions, and how to identify pin-1. table 1. signal names signal name function direction c serial clock input d serial data input input q serial data output output s chip select input w write protect input hold hold input v cc supply voltage v ss ground 1 ai04091b 2 3 4 8 7 6 5 d v ss c hold q sv cc w m25p40
signal description m25p40 8/59 2 signal description 2.1 serial data output (q) this output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of serial clock (c). 2.2 serial data input (d) this input signal is used to transfer data serially into the device. it receives instructions, addresses, and the data to be programmed. values are latched on the rising edge of serial clock (c). 2.3 serial clock (c) this input signal provides the timing of the serial interface. instructions, addresses, or data present at serial data input (d) are latched on the rising edge of serial clock (c). data on serial data output (q) changes after the falling edge of serial clock (c). 2.4 chip select (s ) when this input signal is high, the device is deselected and serial data output (q) is at high impedance. unless an internal program, erase or write status register cycle is in progress, the device will be in the standby power mode (this is not the deep power-down mode). driving chip select (s ) low selects the device, placing it in the active power mode. after power-up, a falling edge on chip select (s ) is required prior to the start of any instruction. 2.5 hold (hold ) the hold (hold ) signal is used to pause any serial communications with the device without deselecting the device. during the hold condition, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don?t care. to start the hold condition, the device must be selected, with chip select (s ) driven low. 2.6 write protect (w ) the main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the bp2, bp1 and bp0 bits of the status register).
m25p40 signal description 9/59 2.7 v cc supply voltage v cc is the supply voltage. 2.8 v ss ground v ss is the reference for the v cc supply voltage.
spi modes m25p40 10/59 3 spi modes these devices can be driven by a microcontroller with its spi peripheral running in either of the two following modes: ? cpol=0, cpha=0 ? cpol=1, cpha=1 for these two modes, input data is latched in on the rising edge of serial clock (c), and output data is available from the falling edge of serial clock (c). the difference between the two modes, as shown in figure 4 , is the clock polarity when the bus master is in stand-by mode and not transferring data: ? c remains at 0 for (cpol=0, cpha=0) ? c remains at 1 for (cpol=1, cpha=1) figure 3. bus master and memory devices on the spi bus 1. the write protect (w ) and hold (hold ) signals should be driven, high or low as appropriate. figure 3 shows an example of three devices connected to an mcu, on an spi bus. only one device is selected at a time, so only one device drives the serial data output (q) line at a time, the other devices are high impedance. resistors r (represented in figure 3 ) ensure that the m25p40 is not selected if the bus master leaves the s line in the high impedance state. as the bus master may enter a state where all inputs/outputs are in high impedance at the same time (for example, when the bus master is reset), the clock line (c) must be connected to an external pull-down resistor so that, when all inputs/outputs become high impedance, the s line is pulled high while the c line is pulled low (thus ensuring that s and c do not become high at the same time, and so, that the t shch requirement is met). the typical value of r is 100 k , assuming that the time constant r*c p (c p = parasitic capacitance of the bus line) is shorter than the time during which the bus master leaves the spi bus in high impedance. ai12836b spi bus master spi memory device sdo sdi sck cqd s spi memory device cqd s spi memory device cqd s cs3 cs2 cs1 spi interface with (cpol, cpha) = (0, 0) or (1, 1) w hold w hold w hold rr r v cc v cc v cc v cc v ss v ss v ss v ss r
m25p40 spi modes 11/59 example: c p = 50 pf, that is r*c p = 5 s <=> the application must ensure that the bus master never leaves the spi bus in the high impedance state for a time period shorter than 5 s. figure 4. spi modes supported ai01438 b c msb cpha d 0 1 cpol 0 1 q c msb
operating features m25p40 12/59 4 operating features 4.1 page programming to program one data byte, two instructions are required: write enable (wren), which is one byte, and a page program (pp) sequence, which consists of four bytes plus data. this is followed by the internal program cycle (of duration t pp ). to spread this overhead, the page program (pp) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory. for optimized timings, it is recommended to use the page program (pp) instruction to program all consecutive targeted bytes in a single sequence versus using several page program (pp) sequences with each containing only a few bytes (see page program (pp) , instruction times, process technology t9hx (device grade 6) and table 17: instruction times (device grade 3) ). 4.2 sector erase and bulk erase the page program (pp) instruction allows bits to be reset from 1 to 0. before this can be applied, the bytes of memory need to have been erased to all 1s (ffh). this can be achieved either a sector at a time, using the sector erase (se) instruction, or throughout the entire memory, using the bulk erase (be) instruction. this starts an internal erase cycle (of duration t se or t be ). the erase instruction must be preceded by a write enable (wren) instruction. 4.3 polling during a write, program or erase cycle a further improvement in the time to write status register (wrsr), program (pp) or erase (se or be) can be achieved by not waiting for the worst case delay (t w , t pp , t se , or t be ). the write in progress (wip) bit is provided in the status register so that the application program can monitor its value, polling it to establish when the previous write cycle, program cycle or erase cycle is complete. 4.4 active power, standby power and deep power-down modes when chip select (s ) is low, the device is selected, and in the active power mode. when chip select (s ) is high, the device is deselected, but could remain in the active power mode until all internal cycles have completed (program, erase, write status register). the device then goes in to the standby power mode. the device consumption drops to i cc1 . the deep power-down mode is entered when the specific instruction (the deep power- down (dp) instruction) is executed. the device consumption drops further to i cc2 . the device remains in this mode until another specific instruction (the release from deep power-down and read electronic signature (res) instruction) is executed.
m25p40 operating features 13/59 all other instructions are ignored while the device is in the deep power-down mode. this can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent write, program or erase instructions. 4.5 status register the status register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. for a detailed description of the status register bits, see section 6.4: read status register (rdsr) . 4.6 protection modes the environments where non-volatile memory devices are used can be very noisy. no spi device can operate correctly in the presence of excessive noise. to help combat this, the m25p40 features the following data protection mechanisms: ? power on reset and an internal timer (t puw ) can provide protection against inadvertent changes while the power supply is outside the operating specification. ? program, erase and write status register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. ? all instructions that modify data must be preceded by a write enable (wren) instruction to set the write enable latch (wel) bit. this bit is returned to its reset state by the following events: ? power-up ? write disable (wrdi) instruction completion ? write status register (wrsr) instruction completion ? page program (pp) instruction completion ? sector erase (se) instruction completion ? bulk erase (be) instruction completion ? the block protect (bp2, bp1, bp0) bits allow part of the memory to be configured as read-only. this is the software protected mode (spm). ? the write protect (w ) signal allows the block protect (bp2, bp1, bp0) bits and status register write disable (srwd) bit to be protected. this is the hardware protected mode (hpm). ? in addition to the low power consumption feature, the deep power-down mode offers extra software protection from inadvertent write, program and erase instructions, as all instructions are ignored except one particular instruction (the release from deep power-down instruction).
operating features m25p40 14/59 4.7 hold condition the hold (hold ) signal is used to pause any serial communications with the device without resetting the clocking sequence. however, taking this signal low does not terminate any write status register, program or erase cycle that is currently in progress. to enter the hold condition, the device must be selected, with chip select (s ) low. the hold condition starts on the falling edge of the hold (hold ) signal, provided that this coincides with serial clock (c) being low (as shown in figure 5 ). the hold condition ends on the rising edge of the hold (hold ) signal, provided that this coincides with serial clock (c) being low. if the falling edge does not coincide with serial clock (c) being low, the hold condition starts after serial clock (c) next goes low. similarly, if the rising edge does not coincide with serial clock (c) being low, the hold condition ends after serial clock (c) next goes low. (this is shown in figure 5 ). during the hold condition, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don?t care. normally, the device is kept selected, with chip select (s ) driven low, for the whole duration of the hold condition. this is to ensure that the state of the internal logic remains unchanged from the moment of entering the hold condition. if chip select (s ) goes high while the device is in the hold condition, this has the effect of resetting the internal logic of the device. to restart communication with the device, it is necessary to drive hold (hold ) high, and then to drive chip select (s ) low. this prevents the device from going back to the hold condition. table 2. protected area sizes status register content memory content bp2 bit bp1 bit bp0 bit protected area unprotected area 0 0 0 none all sectors (1) (eight sectors: 0 to 7) 1. the device is ready to accept a bu lk erase instruction if, and only if, all block protect (bp2, bp1, bp0) are 0. 0 0 1 upper eighth (sector 7) lower seven-eighths (seven sectors: 0 to 6) 0 1 0 upper quarter (two sectors: 6 and 7) lower three-quarters (six sectors: 0 to 5) 0 1 1 upper half (four sectors: 4 to 7) lower half (four sectors: 0 to 3) 1 0 0 all sectors (eight sectors: 0 to 7) none 1 0 1 all sectors (eight sectors: 0 to 7) none 1 1 0 all sectors (eight sectors: 0 to 7) none 1 1 1 all sectors (eight sectors: 0 to 7) none
m25p40 operating features 15/59 figure 5. hold condition activation ai02029 d hold c hold condition (standard use) hold condition (non-standard use)
memory organization m25p40 16/59 5 memory organization the memory is organized as: ? 524,288 bytes (8 bits each) ? 8 sectors (512 kbits, 65536 bytes each) ? 2048 pages (256 bytes each). each page can be individually programmed (bits are programmed from 1 to 0). the device is sector or bulk erasable (bits are erased from 0 to 1) but not page erasable. table 3. memory organization sector address range 7 70000h 7ffffh 6 60000h 6ffffh 5 50000h 5ffffh 4 40000h 4ffffh 3 30000h 3ffffh 2 20000h 2ffffh 1 10000h 1ffffh 0 00000h 0ffffh
m25p40 memory organization 17/59 figure 6. block diagram ai04986 hold s w control logic high voltage generator i/o shift register address register and counter 256 byte data buffer 256 bytes (page size) x decoder y decoder size of the read-only memory are a c d q status register 00000h 7ffffh 000ffh
instructions m25p40 18/59 6 instructions all instructions, addresses and data are shifted in and out of the device, most significant bit first. serial data input (d) is sampled on the first rising edge of serial clock (c) after chip select (s ) is driven low. then, the one-byte instruction code must be shifted in to the device, most significant bit first, on serial data input (d), each bit being latched on the rising edges of serial clock (c). the instruction set is listed in ta bl e 4 . every instruction sequence starts with a one-byte instruction code. depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. chip select (s ) must be driven high after the last bit of the instruction sequence has been shifted in. in the case of a read data bytes (read), read data bytes at higher speed (fast_read), read identification (rdid), read status register (rdsr) or release from deep power- down, and read electronic signature (res) instruction, the shifted-in instruction sequence is followed by a data-out sequence. chip select (s ) can be driven high after any bit of the data-out sequence is being shifted out. in the case of a page program (pp), sector erase (se), bulk erase (be), write status register (wrsr), write enable (wren), write disable (wrdi) or deep power-down (dp) instruction, chip select (s ) must be driven high exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. that is, chip select (s ) must driven high when the number of clock pulses after chip select (s ) being driven low is an exact multiple of eight. all attempts to access the memory array during a write status register cycle, program cycle or erase cycle are ignored, and the internal write status register cycle, program cycle or erase cycle continues unaffected.
m25p40 instructions 19/59 6.1 write enable (wren) the write enable (wren) instruction ( figure 7 ) sets the write enable latch (wel) bit. the write enable latch (wel) bit must be set prior to every page program (pp), sector erase (se), bulk erase (be) and write status register (wrsr) instruction. the write enable (wren) instruction is entered by driving chip select (s ) low, sending the instruction code, and then driving chip select (s ) high. figure 7. write enable (wren) instruction sequence table 4. instruction set instruction description one-byte instruction code address bytes dummy bytes data bytes wren write enable 0000 0110 06h 0 0 0 wrdi write disable 0000 0100 04h 0 0 0 rdid (1) 1. the read identification (rdid) instruction is avail able only in products with process technology code x and 4 (see application note an1995). read identification 1001 1111 9fh 0 0 1 to 3 rdsr read status register 0000 0101 05h 0 0 1 to wrsr write status register 0000 0001 01h 0 0 1 read read data bytes 0000 0011 03h 3 0 1 to fast_read read data bytes at higher speed 0000 1011 0bh 3 1 1 to pp page program 0000 0010 02h 3 0 1 to 256 se sector erase 1101 1000 d8h 3 0 0 be bulk erase 1100 0111 c7h 0 0 0 dp deep power-down 1011 1001 b9h 0 0 0 res release from deep power- down, and read electronic signature 1010 1011 abh 0 3 1 to release from deep power- down 0 0 0 c d ai02281e s q 2 1 34567 high impedance 0 instruction
instructions m25p40 20/59 6.2 write disable (wrdi) the write disable (wrdi) instruction ( figure 8 ) resets the write enable latch (wel) bit. the write disable (wrdi) instruction is entered by driving chip select (s ) low, sending the instruction code, and then driving chip select (s ) high. the write enable latch (wel) bit is reset under the following conditions: ? power-up ? write disable (wrdi) instruction completion ? write status register (wrsr) instruction completion ? page program (pp) instruction completion ? sector erase (se) instruction completion ? bulk erase (be) instruction completion figure 8. write disable (wrdi) instruction sequence c d ai03750d s q 2 1 34567 high impedance 0 instruction
m25p40 instructions 21/59 6.3 read identification (rdid) the read identification (rdid) instruction allows to read the device identification data: ? manufacturer identification (1 byte) ? device identification (2 bytes) a unique id code (uid) (17 bytes, of which 16 available upon customer request). (2) the manufacturer identification is assigned by jedec, and has the value 20h for numonyx. the device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (20h), and the memory capacity of the device in the second byte (13h). the uid contains the length of the following data in the first byte (set to 10h), and 16 bytes of the optional customized factory data (cfd) content. the cfd bytes are read-only and can be programmed with customers data upon their demand. if the customers do not make requests, the devices are shipped with all the cfd bytes programmed to zero (00h). any read identification (rdid) instruction while an erase or program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. the device is first selected by driving chip select (s) low. then, the 8-bit instruction code for the instruction is shifted in. after this, the 24-bit device identification, stored in the memory, the 8-bit cfd length followed by 16 bytes of cfd content will be shifted out on serial data output (q). each bit is shifted out during the falling edge of serial clock (c). the instruction sequence is shown in figure 9 . the read identification (rdid) instruction is terminated by driving chip select (s ) high at any time during data output. when chip select (s ) is driven high, the device is put in the stand-by power mode. once in the stand-by power mode, the device waits to be selected, so that it can receive, decode and execute instructions. 2. the uid feature is available only for process technology t9hx devices, identified by with process identification digit "4" in the device marking and process letter "b" in the part number. table 5. read identification (rdid) data-out sequence manufacturer identification device identification uid memory type memory capacity cfd length cfd content 20h 20h 13h 10h 16 bytes
instructions m25p40 22/59 figure 9. read identification (rdid) instruction sequence and data-out sequence 6.4 read status register (rdsr) the read status register (rdsr) instruction allows the status register to be read. the status register may be read at any time, even while a program, erase or write status register cycle is in progress. when one of these cycles is in progress, it is recommended to check the write in progress (wip) bit before sending a new instruction to the device. it is also possible to read the status register continuously, as shown in figure 10 . the status and control bits of the status register are as follows: 6.4.1 wip bit the write in progress (wip) bit indicates whether the memory is busy with a write status register, program or erase cycle. when set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress. 6.4.2 wel bit the write enable latch (wel) bit indicates the status of the internal write enable latch. when set to 1 the internal write enable latch is set, when set to 0 the internal write enable latch is reset and no write status register, program or erase instruction is accepted. c d s 2 1 3456789101112131415 instruction 0 ai06809b q manufacturer identification high impedance msb 15 1413 3210 device identification msb 16 17 18 28 29 30 31 table 6. status register format b7 b0 srwd 0 0 bp2 bp1 bp0 wel wip status register write protect block protect bits write enable latch bit write in progress bit
m25p40 instructions 23/59 6.4.3 bp2, bp1, bp0 bits the block protect (bp2, bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against program and erase instructions. these bits are written with the write status register (wrsr) instruction. when one or more of the block protect (bp2, bp1, bp0) bits is set to 1, the relevant memory area (as defined in ta bl e 2 ) becomes protected against page program (pp) and sector erase (se) instructions. the block protect (bp2, bp1, bp0) bits can be written provided that the hardware protected mode has not been set. the bulk erase (be) instruction is executed if, and only if, all block protect (bp2, bp1, bp0) bits are 0. 6.4.4 srwd bit the status register write disable (srwd) bit is operated in conjunction with the write protect (w ) signal. the status register write disable (srwd) bit and write protect (w ) signal allow the device to be put in the hardware protected mode (when the status register write disable (srwd) bit is set to 1, and write protect (w ) is driven low). in this mode, the non-volatile bits of the status register (srwd, bp2, bp1, bp0) become read-only bits and the write status register (wrsr) instruction is no longer accepted for execution. figure 10. read status register (rdsr) instruction sequence and data-out sequence c d s 2 1 3456789101112131415 instruction 0 ai02031e q 7 6543210 status register out high impedance msb 7 6543210 status register out msb 7
instructions m25p40 24/59 6.5 write status register (wrsr) the write status register (wrsr) instruction allows new values to be written to the status register. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded and executed, the device sets the write enable latch (wel). the write status register (wrsr) instruction is entered by driving chip select (s ) low, followed by the instruction code and the data byte on serial data input (d). the instruction sequence is shown in figure 11 . the write status register (wrsr) instruction has no effect on b6, b5, b1 and b0 of the status register. b6 and b5 are always read as 0. chip select (s ) must be driven high after the eighth bit of the data byte has been latched in. if not, the write status register (wrsr) instruction is not executed. as soon as chip select (s ) is driven high, the self-timed write status register cycle (whose duration is t w ) is initiated. while the write status register cycle is in progress, the status register may still be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed write status register cycle, and is 0 when it is completed. when the cycle is completed, the write enable latch (wel) is reset. the write status register (wrsr) instruction allows the user to change the values of the block protect (bp2, bp1, bp0) bits, to define the size of the area that is to be treated as read-only, as defined in ta bl e 2 . the write status register (wrsr) instruction also allows the user to set or reset the status register write disable (srwd) bit in accordance with the write protect (w ) signal. the status register write disable (srwd) bit and write protect (w ) signal allow the device to be put in the hardware protected mode (hpm). the write status register (wrsr) instruction is not executed once the hardware protected mode (hpm) is entered. figure 11. write status register (wrsr) instruction sequence c d ai02282d s q 2 1 3456789101112131415 high impedance instruction status register in 0 765432 0 1 msb
m25p40 instructions 25/59 the protection features of the device are summarized in ta bl e 7 . when the status register write disable (srwd) bit of the status register is 0 (its initial delivery state), it is possible to write to the status register provided that the write enable latch (wel) bit has previously been set by a write enable (wren) instruction, regardless of the whether write protect (w ) is driven high or low. when the status register write disable (srwd) bit of the status register is set to 1, two cases need to be considered, depending on the state of write protect (w ): ? if write protect (w ) is driven high, it is possible to write to the status register provided that the write enable latch (wel) bit has previously been set by a write enable (wren) instruction. ? if write protect (w ) is driven low, it is not possible to write to the status register even if the write enable latch (wel) bit has previously been set by a write enable (wren) instruction. (attempts to write to the status register are rejected, and are not accepted for execution). as a consequence, all the data bytes in the memory area that are software protected (spm) by the block protect (bp2, bp1, bp0) bits of the status register, are also hardware protected against data modification. regardless of the order of the two events, the hardware protected mode (hpm) can be entered: ? by setting the status register write disable (srwd) bit after driving write protect (w ) low ? or by driving write protect (w ) low after setting the status register write disable (srwd) bit. the only way to exit the hardware protected mode (hpm) once entered is to pull write protect (w ) high. if write protect (w ) is permanently tied high, the hardware protected mode (hpm) can never be activated, and only the software protected mode (spm), using the block protect (bp2, bp1, bp0) bits of the status register, can be used. table 7. protection modes w signal srwd bit mode write protection of the status register memory content protected area (1) 1. as defined by the values in the block protect (bp2, bp1, bp0) bits of the status register, as shown in table 2. unprotected area (1) 10 software protected (spm) status register is writable (if the wren instruction has set the wel bit) the values in the srwd, bp2, bp1 and bp0 bits can be changed protected against page program, sector erase and bulk erase ready to accept page program and sector erase instructions 00 11 01 hardware protected (hpm) status register is hardware write protected the values in the srwd, bp2, bp1 and bp0 bits cannot be changed protected against page program, sector erase and bulk erase ready to accept page program and sector erase instructions
instructions m25p40 26/59 6.6 read data bytes (read) the device is first selected by driving chip select (s ) low. the instruction code for the read data bytes (read) instruction is followed by a 3-byte address (a23-a0), each bit being latched-in during the rising edge of serial clock (c). then the memory contents, at that address, is shifted out on serial data output (q), each bit being shifted out, at a maximum frequency f r , during the falling edge of serial clock (c). the instruction sequence is shown in figure 12 . the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. the whole memory can, therefore, be read with a single read data bytes (read) instruction. when the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. the read data bytes (read) instruction is terminated by driving chip select (s ) high. chip select (s ) can be driven high at any time during data output. any read data bytes (read) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 12. read data bytes (read) instruction sequence and data-out sequence 1. address bits a23 to a19 are don?t care. c d ai03748 d s q 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 76543 1 7 0 high impedance data out 1 instruction 24-bit address 0 msb msb 2 39 data out 2
m25p40 instructions 27/59 6.7 read data bytes at higher speed (fast_read) the device is first selected by driving chip select (s ) low. the instruction code for the read data bytes at higher speed (fast_read) instruction is followed by a 3-byte address (a23- a0) and a dummy byte, each bit being latched-in during the rising edge of serial clock (c). then the memory contents, at that address, is shifted out on serial data output (q), each bit being shifted out, at a maximum frequency f c , during the falling edge of serial clock (c). the instruction sequence is shown in figure 13 . the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. the whole memory can, therefore, be read with a single read data bytes at higher speed (fast_read) instruction. when the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. the read data bytes at higher speed (fast_read) instruction is terminated by driving chip select (s ) high. chip select (s ) can be driven high at any time during data output. any read data bytes at higher speed (fast_read) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 13. read data bytes at higher speed (fast_read) instruction sequence and data-out sequence 1. address bits a23 to a19 are don?t care. c d ai04006 s q 23 2 1 345678910 28293031 2221 3210 high impedance instruction 24 bit address 0 c d s q 32 33 34 36 37 38 39 40 41 42 43 44 45 46 765432 0 1 data out 1 dummy byte msb 7 6543210 data out 2 msb msb 7 47 765432 0 1 35
instructions m25p40 28/59 6.8 page program (pp) the page program (pp) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the page program (pp) instruction is entered by driving chip select (s ) low, followed by the instruction code, three address bytes and at least one data byte on serial data input (d). if the 8 least significant address bits (a7-a0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (a7-a0) are all zero). chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 14 . if more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. if less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. for optimized timings, it is recommended to use the page program (pp) instruction to program all consecutive targeted bytes in a single sequence versus using several page program (pp) sequences with each containing only a few bytes (see instruction times, process technology t9hx (device grade 6) and table 17: instruction times (device grade 3) ). chip select (s ) must be driven high after the eighth bit of the last data byte has been latched in, otherwise the page program (pp) instruction is not executed. as soon as chip select (s ) is driven high, the self-timed page program cycle (whose duration is t pp ) is initiated. while the page program cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed page program cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a page program (pp) instruction applied to a page which is protected by the block protect (bp2, bp1, bp0) bits (see table 3 and ta bl e 2 ) is not executed.
m25p40 instructions 29/59 figure 14. page program (pp) instruction sequence 1. address bits a23 to a19 are don?t care. c d ai04082b s 42 41 43 44 45 46 47 48 49 50 52 53 54 55 40 c d s 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 instruction 24-bit address 0 765432 0 1 data byte 1 39 51 765432 0 1 data byte 2 765432 0 1 data byte 3 data byte 256 2079 2078 2077 2076 2075 2074 2073 765432 0 1 2072 msb msb msb msb msb
instructions m25p40 30/59 6.9 sector erase (se) the sector erase (se) instruction sets to 1 (ffh) all bits inside the chosen sector. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the sector erase (se) instruction is entered by driving chip select (s ) low, followed by the instruction code, and three address bytes on serial data input (d). any address inside the sector (see table 3 ) is a valid address for the sector erase (se) instruction. chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 15 . chip select (s ) must be driven high after the eighth bit of the last address byte has been latched in, otherwise the sector erase (se) instruction is not executed. as soon as chip select (s ) is driven high, the self-timed sector erase cycle (whose duration is t se ) is initiated. while the sector erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed sector erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a sector erase (se) instruction applied to a page which is protected by the block protect (bp2, bp1, bp0) bits (see table 3 and ta bl e 2 ) is not executed. figure 15. sector erase (se) instruction sequence 1. address bits a23 to a19 are don?t care. 24 bit address c d ai03751d s 2 1 3456789 293031 instruction 0 23 22 2 0 1 msb
m25p40 instructions 31/59 6.10 bulk erase (be) the bulk erase (be) instruction sets all bits to 1 (ffh). before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the bulk erase (be) instruction is entered by driving chip select (s ) low, followed by the instruction code on serial data input (d). chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 16 . chip select (s ) must be driven high after the eighth bit of the instruction code has been latched in, otherwise the bulk erase instruction is not executed. as soon as chip select (s ) is driven high, the self-timed bulk erase cycle (whose duration is t be ) is initiated. while the bulk erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed bulk erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. the bulk erase (be) instruction is executed only if all block protect (bp2, bp1, bp0) bits are 0. the bulk erase (be) instruction is ignored if one, or more, sectors are protected. figure 16. bulk erase (be) instruction sequence c d ai03752d s 2 1 34567 0 instruction
instructions m25p40 32/59 6.11 deep power-down (dp) executing the deep power-down (dp) instruction is the only way to put the device in the lowest consumption mode (the deep power-down mode). it can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all write, program and erase instructions. driving chip select (s ) high deselects the device, and puts the device in the standby power mode (if there is no internal cycle currently in progress). but this mode is not the deep power-down mode. the deep power-down mode can only be entered by executing the deep power-down (dp) instruction, subsequently reducing the standby current (from i cc1 to i cc2 , as specified in table 13 ). once the device has entered the deep power-down mode, all instructions are ignored except the release from deep power-down and read electronic signature (res) instruction. this releases the device from this mode. the release from deep power-down and read electronic signature (res) instruction and the read identification (rdid) instruction also allow the electronic signature of the device to be output on serial data output (q). the deep power-down mode automatically stops at power-down, and the device always powers-up in the standby power mode. the deep power-down (dp) instruction is entered by driving chip select (s ) low, followed by the instruction code on serial data input (d). chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 17 . chip select (s ) must be driven high after the eighth bit of the instruction code has been latched in, otherwise the deep power-down (dp) instruction is not executed. as soon as chip select (s ) is driven high, it requires a delay of t dp before the supply current is reduced to i cc2 and the deep power-down mode is entered. any deep power-down (dp) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 17. deep power-down (dp) instruction sequence c d ai03753d s 2 1 34567 0 t dp deep power-down mode stand-by mode instruction
m25p40 instructions 33/59 6.12 release from deep power-down and read electronic signature (res) once the device has entered the deep power-down mode, all instructions are ignored except the release from deep power-down and read electronic signature (res) instruction. executing this instruction takes the device out of the deep power-down mode. the instruction can also be used to read, on serial data output (q), the 8-bit electronic signature, whose value for the m25p40 is 12h . except while an erase, program or write status register cycle is in progress, the release from deep power-down and read electronic signature (res) instruction always provides access to the 8-bit electronic signature of the device, and can be applied even if the deep power-down mode has not been entered. any release from deep power-down and read electronic signature (res) instruction while an erase, program or write status register cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. the device is first selected by driving chip select (s ) low. the instruction code is followed by 3 dummy bytes, each bit being latched-in on serial data input (d) during the rising edge of serial clock (c). then, the 8-bit electronic signature, stored in the memory, is shifted out on serial data output (q), each bit being shifted out during the falling edge of serial clock (c). the instruction sequence is shown in figure 18 . the release from deep power-down and read electronic signature (res) instruction is terminated by driving chip select (s ) high after the electronic signature has been read at least once. sending additional clock cycles on serial clock (c), while chip select (s ) is driven low, cause the electronic signature to be output repeatedly. when chip select (s ) is driven high, the device is put in the standby power mode. if the device was not previously in the deep power-down mode, the transition to the standby power mode is immediate. if the device was previously in the deep power-down mode, though, the transition to the standby power mode is delayed by t res2 , and chip select (s ) must remain high for at least t res2 (max), as specified in ta bl e 1 9 . once in the standby power mode, the device waits to be selected, so that it can receive, decode and execute instructions. driving chip select (s ) high after the 8 - bit instruction byte has been received by the device, but before the whole of the 8-bit electronic signature has been transmitted for the first time (as shown in figure 19 ), still ensures that the device is put into standby power mode. if the device was not previously in the deep power-down mode, the transition to the standby power mode is immediate. if the device was previously in the deep power-down mode, though, the transition to the standby power mode is delayed by t res1 , and chip select (s ) must remain high for at least t res1 (max), as specified in ta bl e 1 9 . once in the standby power mode, the device waits to be selected, so that it can receive, decode and execute instructions.
instructions m25p40 34/59 figure 18. release from deep power-down and read electronic signature (res) instruction sequence and data-out sequence 1. the value of the 8-bit electronic signature, for the m25p40, is 12h. figure 19. release from deep power-down (res) instruction sequence c d ai04047c s q 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 765432 0 1 high impedance electronic signature out instruction 3 dummy bytes 0 msb stand-by mode deep power-down mode msb t res2 c d ai04078b s 2 1 34567 0 t res1 stand-by mode deep power-down mode q high impedance instruction
m25p40 power-up and power-down 35/59 7 power-up and power-down at power-up and power-down, the device must not be selected (that is chip select (s ) must follow the voltage applied on v cc ) until v cc reaches the correct value: ? v cc (min) at power-up, and then for a further delay of t vsl ? v ss at power-down a safe configuration is provided in section 3: spi modes . to avoid data corruption and inadvertent write operations during power-up, a power on reset (por) circuit is included. the logic inside the device is held reset while v cc is less than the power on reset (por) threshold voltage, v wi ? all operations are disabled, and the device does not respond to any instruction. moreover, the device ignores all write enable (wren), page program (pp), sector erase (se), bulk erase (be) and write status register (wrsr) instructions until a time delay of t puw has elapsed after the moment that v cc rises above the v wi threshold. however, the correct operation of the device is not guaranteed if, by this time, v cc is still below v cc (min). no write status register, program or erase instructions should be sent until the later of: ? t puw after v cc passed the v wi threshold ? t vsl after v cc passed the v cc (min) level these values are specified in table 9 . if the delay, t vsl , has elapsed, after v cc has risen above v cc (min), the device can be selected for read instructions even if the t puw delay is not yet fully elapsed. at power-up, the device is in the following state: ? the device is in the standby power mode (not the deep power-down mode). ? the write enable latch (wel) bit is reset. ? the write in progress (wip) bit is reset. normal precautions must be taken for supply rail decoupling, to stabilize the v cc supply. each device in a system should have the v cc rail decoupled by a suitable capacitor close to the package pins. (generally, this capacitor is of the order of 100 nf). at power-down, when v cc drops from the operating voltage, to below the power on reset (por) threshold voltage, v wi , all operations are disabled and the device does not respond to any instruction. (the designer needs to be aware that if a power-down occurs while a write, program or erase cycle is in progress, some data corruption can result.)
power-up and power-down m25p40 36/59 figure 20. power-up timing table 8. power-up timing and v wi threshold symbol parameter min. max. unit t vsl (1) 1. these parameters are characterized only. v cc (min) to s low 10 s t puw (1) time delay to write instruction 1 10 ms v wi (1) write inhibit voltage (device grade 6) 1 2.1 v write inhibit voltage (device grade 3) 2.1 2.1 v v cc ai04009c v cc (min) v wi reset state of the device chip selection not allowed program, erase and write commands are rejected by the device tvsl tpuw time read access allowed device fully accessible v cc (max)
m25p40 initial delivery state 37/59 8 initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh). the status register contains 00h (all status register bits are 0). 9 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the numonyx sure program and other relevant quality documents. table 9. absolute maximum ratings symbol parameter min. max. unit t stg storage temperature ?65 150 c t lead lead temperature during soldering see (1) 1. compliant with jedec std j-std-020c (for small body, sn-pb or pb assembly), the st ecopack? 7191395 specification, and the european directive on restrictions on hazardous substances (rohs) 2002/95/eu. c v io input and output voltage (with respect to ground) (2) 2. the minimum voltage may reach the value of -2 v for no more than 20 ns during transitions; the maximum voltage may reach the value of v cc +2 v for no more than 20 ns during transitions.. ?0.6 v cc + 0.6 v v cc supply voltage ?0.6 4.0 v v esd electrostatic discharge voltage (human body model) (3) 3. jedec std jesd22-a114a (c1 = 100 pf, r1 = 1500 , r2 = 500 ). ?2000 2000 v
dc and ac parameters m25p40 38/59 10 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. table 10. operating conditions symbol parameter min. max. unit v cc supply voltage 2.3 3.6 v t a ambient operating temperature (device grade 6) ?40 85 c ambient operating temperature (device grade 3) ?40 125 table 11. data retention and endurance parameter condition min. max. unit erase/program cycles device grade 6 100,000 cycles per sector device grade 3 10,000 data retention at 55c 20 years table 12. capacitance (1) 1. sampled only, not 100% tested, at t a =25 c and a frequency of 25 mhz. symbol parameter test condition min. max. unit c out output capacitance (q) v out = 0 v 8 pf c in input capacitance (other pins) v in = 0 v 6 pf
m25p40 dc and ac parameters 39/59 table 13. dc characteristics (device grade 6) symbol parameter test condition (in addition to those in table 10 ) min. max. unit i li input leakage current 2 a i lo output leakage current 2 a i cc1 standby current s = v cc , v in = v ss or v cc 50 a i cc2 deep power-down current s = v cc , v in = v ss or v cc 10 a i cc3 operating current (read) c = 0.1v cc / 0.9.v cc at 40 mhz and 75 mhz, q = open 8ma c = 0.1v cc / 0.9.v cc at 25 mhz, q = open 4ma i cc4 operating current (pp) s = v cc 15 ma i cc5 operating current (wrsr) s = v cc 15 ma i cc6 operating current (se) s = v cc 15 ma i cc7 operating current (be) s = v cc 15 ma v il input low voltage ?0.5 0.3v cc v v ih input high voltage 0.7v cc v cc +0.4 v v ol output low voltage i ol = 1.6 ma 0.4 v v oh output high voltage i oh = ?100 av cc ?0.2 v
dc and ac parameters m25p40 40/59 table 14. dc characteristics (device grade 3) symbol parameter test condition (in addition to those in table 10 ) min (1) 1. this is preliminary data. max (1) unit i li input leakage current 2 a i lo output leakage current 2 a i cc1 standby current s = v cc , v in = v ss or v cc 100 a i cc2 deep power-down current s = v cc , v in = v ss or v cc 50 a i cc3 operating current (read) c = 0.1v cc / 0.9.v cc at 25 mhz, q = open 8ma c = 0.1v cc / 0.9.v cc at 20 mhz, q = open 4ma i cc4 operating current (pp) s = v cc 15 ma i cc5 operating current (wrsr) s = v cc 15 ma i cc6 operating current (se) s = v cc 15 ma i cc7 operating current (be) s = v cc 15 ma v il input low voltage ? 0.5 0.3v cc v v ih input high voltage 0.7v cc v cc +0.4 v v ol output low voltage i ol = 1.6 ma 0.4 v v oh output high voltage i oh = ?100 av cc ?0.2 v table 15. instruction times, process technology t9hx (1) (device grade 6) 1. technology t9hx devices are identified by process identification digit "4" in the device marking and process letter "b" in the part number . test conditions specified in table 10 and table 18 symbol alt. parameter min. typ. max. unit t w write status register cycle time 1.3 15 ms t pp (2) 2. when using the page program (pp) instruction to program consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes. (1 n 256) page program cycle time (256 bytes) 0.8 5ms page program cycle time (n bytes) int (n/8) 0.025 (2) t se sector erase cycle time 0.6 3 s t be bulk erase cycle time 4.5 10 s
m25p40 dc and ac parameters 41/59 1. output hi-z is defined as the point where data out is no longer driven. table 16. instruction times, process technology t7y (1) (device grade 6) 1. technology t7y devices are identified by process identification digit "x" in the device marking. test conditions specified in table 10 and table 18 symbol alt. parameter min. typ. max. unit t w write status register cycle time 5 15 ms t pp (2) 2. when using the page program (pp) instruction to program consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes. (1 n 256) page program cycle time (256 bytes) 1.4 5ms page program cycle time (n bytes) 0.4+n*1/ 256 (2) t se sector erase cycle time 1 3 s t be bulk erase cycle time 4.5 10 s table 17. instruction times (device grade 3) test conditions specified in table 10 and table 18 symbol alt. parameter min. typ. (1) (2) 1. at 85 c 2. preliminary data. max. (2) unit t w write status register cycle time 8 15 ms t pp (3) 3. when using the page program (pp) instruction to program consecutive bytes, optimized timings are obtained with one sequence including all the bytes ve rsus several sequences of only a few bytes. (1 n 256) page program cycle time (256 bytes) 1.5 5ms page program cycle time (n bytes) 0.4+ n*1.1/256 t se sector erase cycle time 1 3 s t be bulk erase cycle time 4.5 10 s table 18. ac measurement conditions symbol parameter min. max. unit c l load capacitance 30 pf input rise and fall times 5 ns input pulse voltages 0.2v cc to 0.8v cc v input timing reference voltages 0.3v cc to 0.7v cc v output timing reference voltages v cc / 2 v
dc and ac parameters m25p40 42/59 figure 21. ac measurement i/o waveform ai07455 0 .8v cc 0 .2v cc 0.7v c c 0.3v c c input and outp ut timing reference leve ls i nput levels 0.5v c c
m25p40 dc and ac parameters 43/59 table 19. ac characteristics (25 mhz operation, device grade 3, v cc min = 2.7 v) test conditions specified in table 10 and table 18 symbol alt. parameter min. typ. max. unit f c f c clock frequency for the following instructions: fast_read, pp, se, be, dp, res, wren, wrdi, rdsr, wrsr d.c. 25 mhz f r clock frequency for read instructions d.c. 20 mhz t ch (1) 1. t ch + t cl must be greater than or equal to 1/ f c t clh clock high time 18 ns t cl (1) t cll clock low time 18 ns t clch (2) 2. value guaranteed by characterization, not 100% tested in production. clock rise time (3) (peak to peak) 3. expressed as a slew-rate. 0.1 v/ns t chcl (2) clock fall time (3) (peak to peak) 0.1 v/ns t slch t css s active setup time (relative to c) 10 ns t chsl s not active hold time (relative to c) 10 ns t dvch t dsu data in setup time 5 ns t chdx t dh data in hold time 5 ns t chsh s active hold time (relative to c) 10 ns t shch s not active setup time (relative to c) 10 ns t shsl t csh s deselect time 100 ns t shqz (2) t dis output disable time 15 ns t clqv t v clock low to output valid 15 ns t clqx t ho output hold time 0 ns t hlch hold setup time (relative to c) 10 ns t chhh hold hold time (relative to c) 10 ns t hhch hold setup time (relative to c) 10 ns t chhl hold hold time (relative to c) 10 ns t hhqx (2) t lz hold to output low-z 15 ns t hlqz (2) t hz hold to output high-z 20 ns t whsl (4) 4. only applicable as a constraint for a wrsr instruction when srwd is set at 1. write protect setup time 20 ns t shwl (4) write protect hold time 100 ns t dp (2) s high to deep power-down mode 3 s t res1 (2) s high to standby power mode without electronic signature read 3 or 30 (5) 5. it is 30 s in devices produced with the ?x? process techno logy (grade 3 devices are only produced using the ?x? process technology). details of how to find the process letter on the device marking are given in the application note an1995. s t res2 (2) s high to standby power mode with electronic signature read 1.8 or 30 (5) s
dc and ac parameters m25p40 44/59 table 20. ac characteristics (50 mhz operation, device grade 6, v cc min = 2.7 v) test conditions specified in table 10 and table 18 symbol alt. parameter min. typ. max. unit f c f c clock frequency for the following instructions: fast_read, pp, se, be, dp, res, wren, rdid, wrdi, rdsr, wrsr d.c. 50 mhz f r clock frequency for read instructions d.c. 25 mhz t ch (1) 1. t ch + t cl must be greater than or equal to 1/ f c t clh clock high time 9 ns t cl (1) t cll clock low time 9 ns t clch (2) 2. value guaranteed by characterization, not 100% tested in production. clock rise time (3) (peak to peak) 3. expressed as a slew-rate. 0.1 v/ns t chcl (2) clock fall time (3) (peak to peak) 0.1 v/ns t slch t css s active setup time (relative to c) 5 ns t chsl s not active hold time (relative to c) 5 ns t dvch t dsu data in setup time 2 ns t chdx t dh data in hold time 5 ns t chsh s active hold time (relative to c) 5 ns t shch s not active setup time (relative to c) 5 ns t shsl t csh s deselect time 100 ns t shqz (2) t dis output disable time 8 ns t clqv t v clock low to output valid 8 ns t clqx t ho output hold time 0 ns t hlch hold setup time (relative to c) 5 ns t chhh hold hold time (relative to c) 5 ns t hhch hold setup time (relative to c) 5 ns t chhl hold hold time (relative to c) 5 ns t hhqx (2) t lz hold to output low-z 8 ns t hlqz (2) t hz hold to output high-z 8 ns t whsl (4) 4. only applicable as a constraint for a wrsr instruction when srwd is set at 1. write protect setup time 20 ns t shwl (4) write protect hold time 100 ns t dp (2) s high to deep power-down mode 3 s t res1 (2) s high to standby power mode without electronic signature read 30 s t res2 (2) s high to standby power mode with electronic signature read 30 s
m25p40 dc and ac parameters 45/59 table 21. ac characteristics (*40 mhz operation, device grade 6, v cc min = 2.3 v) extended v cc range available only in products with process technology code x and 4 (1) test conditions specified in table 10 and table 18 1. details of how to find the date of marking are given in application note, an1995 . symbol alt. parameter min. typ. max. unit f c f c clock frequency for the following instructions: fast_read, pp, se, be, dp, res, wren, rdid, wrdi, rdsr, wrsr d.c. 40 mhz f r clock frequency for read instructions d.c. 25 mhz t ch (2) 2. t ch + t cl must be greater than or equal to 1/ f c t clh clock high time 11 ns t cl (1) t cll clock low time 11 ns t clch (3) 3. value guaranteed by characterization, not 100% tested in production. clock rise time (4) (peak to peak) 4. expressed as a slew-rate. 0.1 v/ns t chcl (2) clock fall time (3) (peak to peak) 0.1 v/ns t slch t css s active setup time (relative to c) 5 ns t chsl s not active hold time (relative to c) 5 ns t dvch t dsu data in setup time 2 ns t chdx t dh data in hold time 5 ns t chsh s active hold time (relative to c) 5 ns t shch s not active setup time (relative to c) 5 ns t shsl t csh s deselect time 100 ns t shqz (2) t dis output disable time 8 ns t clqv t v clock low to output valid 8 ns t clqx t ho output hold time 0 ns t hlch hold setup time (relative to c) 5 ns t chhh hold hold time (relative to c) 5 ns t hhch hold setup time (relative to c) 5 ns t chhl hold hold time (relative to c) 5 ns t hhqx (2) t lz hold to output low-z 8 ns t hlqz (2) t hz hold to output high-z 8 ns t whsl (5) 5. only applicable as a constraint for a wrsr instruction when srwd is set at 1. note: *40 mhz = max frequency device operation in extended vcc range 2.3 to 2.7 v. write protect setup time 20 ns t shwl (4) write protect hold time 100 ns t dp (2) s high to deep power-down mode 3 s t res1 (2) s high to standby power mode without electronic signature read 30 s t res2 (2) s high to standby power mode with electronic signature read 30 s
dc and ac parameters m25p40 46/59 table 22. ac characteristics, grade 6 ( t9hx technology ), 75 mhz operation, vcc min = 2.7 v applies only to products made with t9hx technology, identified with process digit ?4? and process letter ?b? in the part number (1) (2) test conditions specified in table 10 and table 12 symbol alt. parameter min typ (3) max unit f c f c clock frequency for the following instructions: fast_read, pp, se, be, dp, res, wren, wrdi, rdid, rdsr, wrsr d.c. 75 mhz f r clock frequency for read instructions d.c. 33 mhz t ch (4) t clh clock high time 6 ns t cl (3) t cll clock low time 6 ns t clch (5) clock rise time (6) (peak to peak) 0.1 v/ns t chcl (5) clock fall time (6) (peak to peak) 0.1 v/ns t slch t css s active setup time (relative to c) 5 ns t chsl s not active hold time (relative to c) 5 ns t dvch t dsu data in setup time 2 ns t chdx t dh data in hold time 5 ns t chsh s active hold time (relative to c) 5 ns t shch s not active setup time (relative to c) 5 ns t shsl t csh s deselect time 100 ns t shqz (5) t dis output disable time 8 ns t clqv t v clock low to output valid under 30 pf/10 pf 8/6 ns t clqx t ho output hold time 0 ns t hlch hold setup time (relative to c) 5 ns t chhh hold hold time (relative to c) 5 ns t hhch hold setup time (relative to c) 5 ns t chhl hold hold time (relative to c) 5 ns t hhqx (5) t lz hold to output low-z 8 ns t hlqz (5) t hz hold to output high-z 8 ns t whsl (7) write protect setup time 20 ns t shwl (7) write protect hold time 100 ns t dp (5) s high to deep power-down mode 3 s t res1 (5) s high to standby mode without read electronic signature 30 s t res2 (5) s high to standby mode with read electronic signature 30 s
m25p40 dc and ac parameters 47/59 figure 22. serial input timing figure 23. write protect setup and hold timing during wrsr when srwd = 1 1. details of how to find the technology proces s in the marking are given in an1995, see also section 12: part numbering . 2. 75 mhz operation is available only on the vcc range 2.7 v - 3.6 v; the maximum frequency in the extended vcc range 2.3 v to 2.7 v is 40 mhz. 3. typical values given for t a = 25 c. 4. t ch + t cl must be greater than or equal to 1/ f c . 5. value guaranteed by characterization, not 100% tested in production. 6. expressed as a slew-rate. 7. only applicable as a constraint for a wrsr instruction when srwd is set at ?1?. c d s msb in q tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl c d s q high impedance w twhsl tshwl ai07439
dc and ac parameters m25p40 48/59 figure 24. hold timing figure 25. output timing c q ai02032 s d hold tchhl thlch thhch tchhh thhqx thlqz c q ai01449 e s lsb out d addr. lsb in tshqz tch tcl tqlqh tqhql tclqx tclqv tclqx tclqv
m25p40 package mechanical 49/59 11 package mechanical 40 mhz is the maximum frequency for the devices operation in the extended vcc range 2.3 v to 2.7 v. figure 26. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package outline 1. drawing is not to scale. 2. the ?1? that appears in the top view of the package shows the position of pin 1. table 23. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package mechanical data symbol millimeters inches typ min max typ min max a 1.75 0.069 a1 0.10 0.25 0.004 0.010 a2 1.25 0.049 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.009 ccc 0.10 0.004 d 4.90 4.80 5.00 0.193 0.189 0.197 e 6.00 5.80 6.20 0.236 0.228 0.244 e1 3.90 3.80 4.00 0.154 0.150 0.157 e 1.27 ? ? 0.050 ? ? h 0.25 0.50 0.010 0.020 k0808 l 0.40 1.27 0.016 0.050 l1 1.04 0.041 so-a e1 8 ccc b e a d c 1 e h x 45? a2 k 0.25 mm l l1 a1 gauge plane
package mechanical m25p40 50/59 figure 27. so8w ? 8 lead plastic small outline, 208 mils body width, package outline 1. drawing is not to scale. table 24. so8 wide ? 8 lead plastic small outline, 208 mils body width, package mechanical data symbol millimeters inches typ min max typ min max a 2.50 0.098 a1 0.00 0.25 0.000 0.010 a2 1.51 2.00 0.059 0.079 b 0.40 0.35 0.51 0.016 0.014 0.020 c 0.20 0.10 0.35 0.008 0.004 0.014 cp 0.10 0.004 d 6.05 0.238 e 5.02 6.22 0.198 0.245 e1 7.62 8.89 0.300 0.350 e 1.27 ? ? 0.050 ? ? k 0 10 0 10 l 0.50 0.80 0.020 0.031 n8 8 6l_me e n cp b e a2 d c l a1 k e1 a 1
m25p40 package mechanical 51/59 figure 28. qfn8l (mlp8) 8-lead, dual flat package no lead, 6 5 mm, package outline 1. drawing is not to scale. table 25. qfn8l (mlp8) 8-lead dual flat package no lead, 6 x 5 mm package mechanical data symbol millimeters inches typ min max typ min max a 0.90 0.80 1.00 0.035 0.031 0.039 a1 0.02 0.00 0.05 0.001 0.000 0.002 a3 0.20 0.008 b 0.40 0.35 0.48 0.016 0.014 0.019 d 6.00 0.236 d2 3.00 2.80 3.20 0.118 0.110 0.126 e 5.00 0.197 e2 3.00 2.80 3.20 0.118 0.110 0.126 e 1.27 0.050 l 0.60 0.50 0.75 0.024 0.020 0.030 0.08 d2 l b 5x_me e2 e e d a a3 a1 e2/2 0pin 1 id option
package mechanical m25p40 52/59 figure 29. vfqfpn8 (mlp8) 8-lead very thin fine pitch quad flat package no lead, 6 5 mm, package outline 1. drawing is not to scale. 2. the circle in the top view of the package indicates the position of pin 1. table 26. vfqfpn8 (mlp8) 8-lead very thin fine pitch quad flat package no lead, 6 5 mm, package mechanical data symbol millimeters inches typ min max typ min max a 0.85 0.80 1.00 0.0335 0.0315 0.0394 a1 0.00 0.05 0.0000 0.0020 a2 0.65 0.0256 a3 0.20 0.0079 b 0.40 0.35 0.48 0.0157 0.0138 0.0189 d 6.00 0.2362 d1 5.75 0.2264 d2 3.40 3.20 3.60 0.1339 0.1260 0.1417 e 5.00 0.1969 e1 4.75 0.1870 e2 4.00 3.80 4.30 0.1575 0.1496 0.1693 e 1.27 ? ? 0.0500 ? ? r1 0.10 0.00 0.0039 0.0000 l 0.60 0.50 0.75 0.0236 0.0197 0.0295 q 12 12 aaa 0.15 0.0059 bbb 0.10 0.0039 ddd 0.05 0.0020 d e 70-m e a2 a a3 a1 e1 d1 e e2 d2 l b r1 ddd bbb c cab aaa ca a b aaa cb m 0.10 ca 0.10 cb 2x
m25p40 part numbering 53/59 12 part numbering table 27. ordering information scheme example: m25p40 ? v mn 6 t p b device type m25p = serial flash memory for code storage device function 40 = 4 mbit (512 k x 8) security features (1) 1. secure options are available upon customer request. ? = no extra security s = cfd programmed with uid operating voltage v = v cc = 2.3 v to 3.6 v package mn = so8 (150 mil width) mp = vfqfpn8 6 x 5 mm (mlp8) mw = so8w (208 mils width) ms = qfn8l (mlp8) (2) , 6 x 5 mm 2. exposed pad of 3 x 3 mm. device grade 6 = industrial temperature range, ?40 to 85 c. device tested with standard test flow 3 (3) = device tested with high reliability certified flow (4) . automotive temperature range (?40 to 125 c) 3. device grade 3 available in an so8 ecopack? (rohs compliant) package. 4. numonyx strongly recommends the use of the automotive grade devices for use in an automotive environment. the high reliability certified flow (hrcf) is described in the quality note qnee9801. please ask your nearest numonyx sales office for a copy. option blank = standard packing t = tape and reel packing plating technology p or g = ecopack? (rohs compliant) process (5) /x = t7y b = t9hx
part numbering m25p40 54/59 for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest numonyx sales office. the category of second-level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. 5. the process letter (/x) is specified in th e ordering information of grade 3 devices only. for grade 6 devices, the process letter does not appear in the ordering information, it only appears on the device package (marking) and on the shipment box. please contact your nearest numonyx sales office. for more information on how to id entify products by the process id entification letter, please refer to an1995: serial flash memory device marking.
m25p40 revision history 55/59 13 revision history table 28. document revision history date revision changes 12-apr-2001 1.0 document written. 25-may-2001 1.1 serial paged flash memory renamed as serial flash memory. 11-sep-2001 1.2 changes to text: signal description/chip select; hold condition/1st para; protection modes; release from power-down and read electronic signature (res); power-up. repositioning of several tables and illustrations without changing their contents. power-up timing illustration; so8w package removed. changes to tables: abs max ratings/v io ; dc characteristics/v il . 16-jan-2002 1.3 fast_read instruction added. document revised with new timings, v wi , i cc3 and clock slew rate. descriptions of polling, hold condition, page programming, release for deep power-down made more precise. value of t w (max) modified. 12-sep-2002 1.4 clarification of descriptions of entering standby power mode from deep power-down mode, and of terminating an instruction sequence or data- out sequence. vfqfpn8 package (mlp8) added. document promoted to preliminary data. 13-dec-2002 1.5 typical page program time improved. deep power-down current changed. write protect setup and hold times specified, for applications that switch write protect to exit the hardware protection mode immediately before a wrsr, and to enter the hardware protection mode again immediately after. 12-jun-2003 1.6 document promoted from preliminary data to full datasheet. 24-nov-2003 2.0 table of contents, warning about exposed paddle on mlp8, and pb-free options added. 40 mhz ac characteristics table included as well as 25 mhz. i cc3 (max), t se (typ) and t be (typ) values improved. change of naming for vdfpn8 package. 12-mar-2004 3.0 automotive range added. soldering temperature information clarified for rohs compliant devices. 05-aug-2004 4.0 device grade information clarified. data-retention measurement temperature corrected. details of how to find the date of marking added. 03-jan-2005 5.0 small text changes. notes 2 and 3 removed from table 27: ordering information scheme . end timing line of t shqz modified in figure 25: output timing . 01-aug-2005 6.0 updated page program (pp) instructions in page programming , page program (pp) , instruction times, process technology t9hx (device grade 6) and instruction times (device grade 3) .
revision history m25p40 56/59 24-oct-2005 7.0 50 mhz operation added (see table 20: ac characteristics (50 mhz operation, device grade 6, vcc min = 2.7 v) ). all packages are ecopack?. blank option removed from under plating technology in table 27: ordering information scheme . mlp package renamed as vfqfpn, silhouette and package mechanical drawing updated (see on page 1 and figure 29: vfqfpn8 (mlp8) 8-lead very thin fine pitch quad flat package no lead, 6 5 mm, package outline . 22-dec-2005 8.0 note 2 added below figure 26 and note 3 added below figure 29 t res1 and t res2 modified in table 20: ac characteristics (50 mhz operation, device grade 6, vcc min = 2.7 v) . read identification (rdid) added. titles of figure 29 and table 26 corrected. 14-apr-2006 9 the data contained in tab le 11 , tab le 17 and table 19 is no longer preliminary data. figure 3: bus master and memory devices on the spi bus modified and note 2 added. 40 mhz frequency condition modified for i cc3 in table 14: dc characteristics (device grade 3) . table 17: instruction times (device grade 3) shows preliminary data. condition changed for the data retention parameter in table 11: data retention and endurance . v wi parameter for device grade 3 added to table 8: power-up timing and vwi threshold . so8 package specifications updated (see figure 26 and tab le 2 3 ). /x process added to table 27: ordering information scheme . 05-jun-2006 10 t res1 and t res2 parameter timings changed for devices produced with the ?x? process technology in tab le 1 9 and tab le 19 . so8 narrow package specifications updated (see figure 26 and tab le 23 ). 18-dec-2006 11 hardware write protection feature added on page 1 . small text changes. section 2.7: vcc supply voltage and section 2.8: vss ground added. figure 3: bus master and memory devices on the spi bus modified, note 2 removed and replaced by explanatory paragraph. wip bit behavior specified at power-up in section 7: power-up and power-down . t lead added to table 9: absolute maximum ratings and v io max modified. vfqfpn8 package specifications updated (see tab le 2 6 and figure 29 ). 25-jan-2007 12 v cc voltage range from w17 2007 is extended to 2.3 v to 3.6 v. table 21: ac characteristics (33 mhz operation, device grade 6, vccmin =2.3 v) added. ac characteristics at 40 mhz removed. 15-may-2007 13 40 mhz operation added (see table 21: ac characteristics (*40 mhz operation, device grade 6, vcc min = 2.3 v) . removed the note below table 10. removed ?ac characteristics (33 mhz operation, device grade 6, vccmin =2.3 v)? table. table 28. document revision history (continued) date revision changes
m25p40 revision history 57/59 26-jun-2007 14 modified the note below ta ble 1 2 . changed test condition for i cc3 in tab le 13 . changed clock frequency, from 20 to 25 mhz, in ta ble 2 0 and tab le 2 1 . 10-dec-2007 15 added numonyx branding. 15-oct-2008 16 changed frequency up to 75 mhz (only in the standard vcc range). added new packages. added uid/cfd protection. extended vcc range to 2.3 v. table 28. document revision history (continued) date revision changes
m25p40 58/58 please read carefully: information in this document is provided in connection with numonyx? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in numonyx's terms and conditions of sale for such products, numonyx assumes no liability whatsoever, and numonyx disclaims any express or implied warranty, relating to sale and/or use of numonyx products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in n uclear facility applications. numonyx may make changes to specifications and product descriptions at any time, without notice. numonyx, b.v. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights th at relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? num onyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. contact your local numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an order number and are referenced in this document, or other numonyx literature may be obtained by visiting numonyx's website at http://www.numonyx.com . numonyx strataflash is a trademark or registered trademark of numonyx or its subsidiaries in the united states and other countr ies. *other names and brands may be claimed as the property of others. copyright ? 2008, numonyx, b.v., all rights reserved.

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